Power-Up Sequence Control for MTCMOS Designs / S.-H. Chen, Y.-L. Lin, M.C.-T. Chao
Architecture and Design Flow for a Highly Efficient Structured ASIC / M.-H. Ho, et al.
Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform / S. Ghosh, D. Mukhopadhay, D. Roychowdhury
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis / J.-W. You, et al.
Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements / S. Kook, H.W. Choi, A. Chatterjee
Low Cost Error Tolerance Scheme for 3-D CMOS Imagers / H.-M. Chang, et al.
Computing Two-Pattern Test Cubes for Transition Path Delay Faults / I Pomeranz
Integated Energy-Harvesting Photodiodes with Diffractive Storage Capacitance / E.G. Fong, et al.
IR Drop in On-Chip Power Distribution Networks of ICs with Nonuniform Power Consuption / J. Rius, et al.
Fast Fixed-Outline 3-D IC Floorplanning with TSV CoPlacement / C.-R. Lo W.-K. Mak, T.C. Wang.
Etc.