This book describes the various test generation algorithms for testing crosstalk
delay faults in VLSI circuits.
Testing is an essential part of any integrated circuit manufacturing system. The
problem of test generation is NP-complete problems, and it is becoming more and
more difficult as system-on-chip designs have approached the deep submicron era.
In addition to the propagation delay, deep submicron technology (DSM) effects will
create severe signal integrity problems. Timing-related defects and signal integrity
problems are introduced by imperfect manufacturing process, process variations,
electromigration, voltage drop in power lines, crosstalk noise, and crosstalk delay
which will cause the chip to fail. Crosstalk delay and crosstalk noise are caused due
to the increased coupling capacitance. As more number of transistors are integrated
on a chip, there is an increase in their aspect ratio and a decrease in the spacing
between the interconnects, and thus, the interconnect coupling capacitances become
larger. This increases the ratio between the coupling capacitance and the total
capacitance leading to an increase in capacitive coupling noise. Crosstalk will
become the major contributor to the interconnect delay in the near future. It is
impossible to estimate the timing faults due to crosstalk delay in the design stage
due to process variations and manufacturing defects. Hence, there is a need for
automatic test pattern generation (ATPG) algorithms that can generate test vectors
for testing the chips for crosstalk delay faults to ensure quality.