Logic Synthesis for VLSI-Based Combined Finite State Machines: Synthesis Targeting ASICs, CPLDs and FPGAs

Logic Synthesis for VLSI-Based Combined Finite State Machines: Synthesis Targeting ASICs, CPLDs and FPGAs
23.21.2205 - Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Ma?gorzata Mazurkiewicz, El?bieta Kawecka