Advanced HDL Synthesis and SOC Prototyping
Vaibbhav Taraate
Informasi Umum
Kode
21.21.705
Klasifikasi
621.3815 - Aerospace engineering. Astronautics. Automotive engineering. Electronic circuits. Transportation.
Jenis
Buku - Elektronik (E-Book)
Subjek
Electronic Circuits And Devices
No. Rak
Tel-U Gedung Manterawu Lantai 5 : Rak 12b
Tel-U Purwokerto : Rak 6
Dilihat
88 kali
Informasi Lainnya
Abstraksi
This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike
Koleksi & Sirkulasi
Tersedia 1 dari total 1 Koleksi
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Pengarang
| Nama | Vaibbhav Taraate |
| Jenis | Perorangan |
| Penyunting | |
| Penerjemah |
Penerbit
| Nama | Springer Singapore |
| Kota | |
| Tahun | 2019 |
Sirkulasi
| Harga sewa | IDR 0,00 |
| Denda harian | IDR 0,00 |
| Jenis | Non-Sirkulasi |
